In prior electronic systems, when a microcontroller or a microprocessor accesses one of external registers, e.g. a register of an IP component, a clock signal and an address signal are first sent to each external register. Each external register decodes the address signal to determine whether the register itself is the access target, followed by the clock signal completing the data access. The clock signal is sent to several flip-flops of the each register; for example, an 8-bit register has 8 flip-flops. When the external registers receive the clock signal, their flip-flops will act, so as to consume the power. However, as a system becomes more complicated including increasingly larger numbers of registers, the system becomes highly power consuming. In particular, if an electronics system is powered by batteries, the power consumption is a critical factor that affects the lifespan of the batteries.
In addition, when a system uses a large number of registers, distances between the microcontroller and various registers create access skew which is unfavorable to data access synchronization. In the prior art, fine tuning of access clocks is required when a microcontroller accesses registers of different distances to balance the effects of the skew. As such, the circuit design complication is increased this way. Further, when a large number of registers are used in a system, the skew is likely to become too complex to fine tune. Therefore, the traditional approach focusing on fine tuning the registers is deficient on keeping both skew and corresponding circuit design uncomplicated and fails to provide an optimal synchronization effect.